The present invention relates to a method for manufacturing LCD (liquid crystal display) of the active matrix type with TFT (thin film transistor) used for a switching element, and more specifically to a method for manufacturing the active matrix type liquid crystal display using TFT (TFT-LCD) with improved display characteristics and productivity by forming the TFT array substrate with little point defect and line defect through five photo-lithography processes.
The LCD, an electro-optic element using liquid crystal, has been popularly applied to displays. In general, the electro-optic element using liquid crystal has a construction in which a liquid crystal layer comprising liquid crystal is interposed between two substrates with electrodes provided on the top and the bottom surfaces, respectively, and in addition, polarizer are installed to the top and bottom of the two substrates, and in the case of a transmissive type, a back-light is provided on the back surface. The surface of the top and bottom substrates provided with the electrode is subject to so-called alignment treatment, and the director which expresses the direction of the liquid crystal molecules in average is controlled to a desired initial state.
The liquid crystal has a property of double refraction, and the light impinged through the polarizer from the back light is changed to an elliptically polarized light by refraction and is impinged on the polarizer on the opposite side. Under this condition, applying voltage across top and bottom electrodes changes the director arrangement condition and changes the double refractive index of the liquid crystal layer, and changes the elliptically polarized light condition impinged on the polarizer on the opposite side, thereby producing an electro-optic effect in that the light intensity and spectrum penetrating the electro-optic element change. This electro-optic effect differs in accord with the type of liquid crystal phase (nematic phase, smectic phase, cholesteric phase, etc.), initial alignment condition, direction of polarization axis of polarizer, thickness of liquid crystal layer, or color filter or various interference films provided on the path on which light penetrates, but these are reported in detail by known references. In general, the construction called TN (twisted nematic) or STN (super twisted nematic) using the nematic liquid crystal phase is employed.
For the electro-optic element for display using liquid crystal, there are simple matrix type LCD and TFT-LCD which uses TFT as a switching element. TFT-LCD which has characteristics superior to CRT or simple matrix type LCD in terms of portability and display quality has been popularly commercialized as notebook-size personal computers, etc. In TFT-LCD, in general, the liquid crystal layer is interposed between the TFT array substrate and opposite substrate. On the TFT array substrate, TFT is formed in a form of array. On the opposite substrate, common electrode and color filter are mounted. On the outside of this kind of TFT array substrate and the opposite substrate, a polarizer is provided, respectively, and in addition, on one side, a back light is provided. With this kind of construction, satisfactory color display is able to be obtained.
However, in TFT-LCD, it is necessary to fabricate the TFT array substrate in which TFT is shaped in the form of array on the glass substrate using the semiconductor technique, and there are problems in that a great number of processes are required and at the same time various defects are likely to occur. For example, in manufacturing TFT-LCD of the VGA (video graphics array) specification, it is necessary to fabricate on the glass substrate at least 921,600 pieces of TFT, 480 pieces of gate line for scanning and choosing each TFT line-sequentially, and 1,920 pieces of source line for providing signal potential for writing in the pixel electrode, and in addition, the gate line and source line are fabricated nearly in the intersecting state. Consequently, there are problems that various display defects are apt to cause display defects including disconnection of gate line, disconnection of source line, short circuit between gate line and source line, defects due to defective TFT, etc. The need for a large number of processes for fabricating TFT not only causes induction of defects but also gives rise to problems of increased number of apparatus necessary for manufacturing and high manufacturing cost.
In addition, for TFT-LCD, because the gate line and source line to be used are generally fabricated by patterning metal thin film, and the line portion does not transmit the light. Consequently, there is a problem in that of the TFT-LCD surface, the ratio of the area in which electro-optic effects can be utilized, that is to say, the aperture ratio, is reduced, and the efficiency for light utilization of the back light is low.
In TFT-LCD, because the parasitic capacity exists in TFT used for switching, a phenomenon in that the display signal is applied from the source line and the potential written to the pixel electrode varies occurs when TFT changes from the ON state to the OFF state. This is a phenomenon called "field through", and the rate of potential change dVgd is expressed as dVgd=(Vgl-Vgh).times.(Cgd/(Cgd+Cpix)) in the case the gate select signal potential (potential of the gate select signal) applied to TFT be Vgh, unselected potential Vgl, parasitic capacity between the TFT gate electrode and drain electrode Cgd, the load capacity of pixel electrode Cpix. When a large DC voltage is applied to the liquid crystal layer, impurities in the liquid crystal may be absorbed to the polyimide film used for alignment, treatment, or polyimide film is subjected to poling, thereby changing the voltage-transmittance characteristics of electro-optic element and giving rise to image tricking of the display. Consequently, the electro-optic element using liquid crystal is driven by the alternate current with voltage polarity applied to the liquid crystal reversed for every frame for line-sequentially of all gate lines, and it is desired to bring the DC potential of the common electrode potential of the opposite substrate to the nearly equivalent level of the DC potential of pixel potential. However, because Cpix contains the liquid crystal capacity and Cpix varies according to the effective voltage applied, dVgd varies according to the display signals, and the DC potential of the pixel potential varies according to the display signals.
As against this, the common electrode of the opposite substrate is the electrode in common to all the pixels and it is natural that the electrode can secure a constant DC potential only, and varying DC potential is applied to the liquid crystal while being dependent on the display signals. The difference d(dVgd) by the display signal of DC potential of this pixel potential becomes maximum between the states with the minimum and the maximum dielectric constants, and when TN or STN is used for the alignment condition of the liquid crystal, it becomes maximum between the display signals applied with the smallest effective voltage and with the largest effective voltage in the display signals.
For a method to reduce d(dVgd) and manufacture displays free of image tricking, there are (1) a method for using TFT with small Cgd or (2) a method for reducing the change rate of Cpix between display signals by adding auxiliary capacity Cs in parallel to the liquid crystal capacity, and others. In order to achieve TFT with small Cgd, it is necessary to reduce the overlap between the pixel electrode of TFT and the drain electrode connected to the gate electrode, giving rise to a problem in that the overlapping accuracy between layers in the patterning process using the photolithography technique (hereinafter called "photolithography process"). In order to add the auxiliary capacity, there needed is a measure either for providing a new auxiliary capacity electrode to the TFT array substrate and bring it to face to the pixel electrode with the insulating film in-between, or to face the pixel electrode with the insulating film put in-between to the gate line scanned one scanning period before than the gate line of the preceding stage, that is, the gate line for scanning a TFT. In the case of the former, there is a problem of a reduced aperture ratio when the auxiliary capacity electrode is formed with metal thin film because an auxiliary capacity electrode is newly provided. In the case of latter, there is a problem of degrading the display quality because the display signals are not sufficiently written in the pixel electrode since the capacity loaded to the gate line increases, delay of gate selection signal occurs, and effective selection time is shortened.
When the TFT array of TFT-LCD is manufactured by divide-exposure with a generally used stepper, since the overlapping condition between layers differ from one divide-exposure region to the other, the parasitic capacity Cgd of TFT varies, and dVgd varies from one divide-exposure region to the other. As a result, since the DC potential of image electrode differs from one divide-exposure region to the other, difference is generated in the effective voltage applied to the liquid crystal, producing a problem of generating so-called variation in shots in which the transmission factor of the electro-optic element using the liquid crystal differs from one divide-exposure region to the other.
For a method to reduce the difference of transmission factor between divide-exposure regions, there are (1) method for improving the interlayer overlapping accuracy between divide-exposure regions to reduce the difference of Cgd between divide-exposure regions, (2) a method for increasing Cgd and reducing the relative change rate of Cgd when an interlayer overlapping difference is generated between divide-exposure region, and (3) a method for adding an auxiliary capacity Cs in parallel to the liquid crystal capacity to increase Cpix and reducing the change of dVgd when Cgd is varied when an interlayer overlapping difference is generated between divide-exposure regions. In order to improve the interlayer overlapping accuracy between divide-exposure regions, there is a problem of improving the positional accuracy of the exposure apparatus or accuracy of photomask. At this point, there is a problem in that it is possible to increase Cgd by increasing the overlapping between the TFT gate and drain electrode connected to the pixel electrode, but image tricking tends to occur because the d(dVgd) increases. In order to add the auxiliary capacity, any of the following measures is required: (1) an auxiliary capacity electrode is newly provided for the TFT array substrate and bring it to face to the pixel electrode with the insulating film put in-between, or (2) the pixel electrode must be faced to the gate line previously scanned and selected with the insulating film put in-between. In the case of the countermeasure (1), because the auxiliary capacity electrode is provided newly, there is a problem of small aperture ratio when the auxiliary electrode capacity is formed using metal thin film. In the case of the countermeasure (2), there is a problem in that the display quality is degraded because the capacity applied to the gate line increases, delay of gate selection signal occurs, the display signal is not sufficiently written in the pixel electrode due to shortened effective selection time, and others.
TFT-LCD has a problem in that the luminance distribution increases in the display element plane because the pixel potential varies due to leak current with TFT in the OFF state during unselected time or leak current to the opposite electrode via the liquid crystal. For a technique to reduce changes of pixel potential during this unselected time, there are methods (1) for increasing OFF resistance of TFT, (2) for increasing electric resistance of liquid crystal, (3) for reducing a change rate of pixel potential by leak current by adding auxiliary capacity Cs in parallel to the liquid capacity to increase Cpix, and others. However, OFF resistance means the resistance between the source electrode and the drain electrode in the case the gate signal is lower than the threshold voltage of TFT (when TFT is in the unselected state). Examples for increasing OFF resistance of TFT include countermeasures (1) for providing the offset structure or LDD (lightly doped domain) region for alleviating the field concentration at the source and drain edges of TFT, (2) for reducing the trap state density inside the band of amorphous silicon film (a-Si film), (3) for reducing the trap state density of the channel interface of the a-Si film and the back channel interface on the opposite side of the channel, (4) for reducing the ratio of channel width W to channel length W/L, and so forth. In order to provide the offset structure or LDD region, a micromachining technique or a technique to accurately control the concentration distribution of impurities to a-Si are required, creating a problem of increasing the complexity of process and structure.
The trap state density in the band of the a-Si film can be reduced by optimizing the film-forming condition or carrying out termination treatment in which hydrogen or fluorine is added to the dangling bond of silicon after film formation. In the known techniques, when the film-forming rate is reduced more than the present film-forming conditions, refined crystallization results, and the OFF resistance is, in turn, reduced, and is possibly in the physical limit state. The latter requires a process for termination treatment in which hydrogen or fluorine is added to silicon dangling bond, giving rise to a problem of complicated process. In order to reduce the trap state density of the channel interface of the a-Si film and the back channel interface opposite to the channel, there taken are countermeasures (1) for optimizing the composition of gate insulating film material and the film forming method, or (2) for optimizing the composition of passivation film material or film-forming method, or others.
These method for improving the OFF characteristics of TFT are reported in detail by known references, but all have problems such as increased complexity of the process. Because to reduce W/L, ratio of channel width W to channel length L, means to reduce the ON current at the same time, there is a problem of degrading the display quality since the display signals are not sufficiently written in the pixel electrode. To increase the resistance of the liquid crystal layer can be achieved by reducing the concentration of impurities of the liquid crystal material or selecting the material which reduces resistance less when moisture or other impurities are taken in, but there still remains a problem in that the pixel potential varies by the leak current in the TFT OFF state. In order to add the auxiliary capacity, any of the following countermeasures is required: (1) to provide the auxiliary capacity electrode newly to the TFT array substrate and allow it to face to the pixel electrode with the insulating film put in-between or (2) to allow the pixel electrode to face to the gate line previously scaned and selected with the insulating film put in-between. In the case of the former, because the auxiliary capacity electrode is provided newly, there is a problem in that the aperture ratio becomes small when the auxiliary capacity electrode is formed by metal thin film. In the case of the latter, there is a problem in that the capacity applied to the gate line increases, delay in gate select signal occurs, the effective select time is shortened, the display signal is, therefore, unable to be sufficiently written in the pixel electrode, and the display quality degrades.
In TFT-LCD, it is necessary to input electrical signals to the gate line, source line, auxiliary capacity line, etc., and these lines must be pulled out to the periphery of the display portion to form a connecting terminal with the signal output. In general, TCP (tape carrier package) with a driving IC loaded is connected to the connection terminal formed on the TFT array substrate using anisotropic conducting film. The TFT array substrate surface of the display portion is isolated from the atmosphere by affixing the circumference of the display portion to the opposite substrate with the adhesives such as epoxy resin, but the TCP connection terminal portion, which is a connecting terminal with TCP, is exposed to the atmosphere. Consequently, there is a problem in that the TCP connecting terminal portion comprising conductive thin film is corroded by the moisture content in the atmosphere.
For these problems, a process for manufacturing TFT array which can reduce the generation of disconnection of source line and at the same time can reduce short-circuiting between the gate line and the source line is disclosed in Japanese Unexamined Patent Publication No. 97386/1985. In addition, a process for manufacturing TFT array for reducing the number of processes and comprising five photolithography process is disclosed in Japanese Unexamined Patent Publication No. 50308/1996. Furthermore, a process for manufacturing TFT array that can improve the moisture resistance at connections between TCP and the connecting terminal is disclosed by Japanese Unexamined Patent Publication No. 92496/1995.
FIG. 16 and FIG. 17 are the cross-sectional illustration of the principal portion and plan illustration of the display pixel of the conventional TFT array substrate disclosed in Japanese Unexamined Patent Publication No. 97386/1995, respectively. In FIG. 16 and FIG. 17, numeral 45 designates a gate electrode, 46 an auxiliary capacity electrode, 47 a gate insulating film, 48 a semiconductor layer, 49 a pixel electrode, 50 a source electrode, 51 a drain electrode, 52 a gate line, 54 a channel portion, and 56 a source line.
In this conventional example, the manufacturing process is not disclosed in detail, but according to the disclosed drawings, it is assumed to be manufactured in the method as described below. First of all, on a insulating substrate, first conductive thin film is formed. Then, in the first photolithography process, the first conductive thin film is patterned and the gate electrode 45 and the auxiliary capacity electrode 46 are formed. Then, the gate insulating film 47 and the semiconductor layer 48 are laminated. Then, in the second photolithography process, the semiconductor layer is patterned in such a manner that a continuous profile is achieved from the portion on which the source electrode 50 is formed to the portion on which the TFT channel is formed, and a semiconductor layer 48 of a desired profile is formed. Then, in the third photolithography process, the second conductive thin film is patterned to form the pixel electrode 49. Next, the third conductive thin film comprising alloys composed with aluminum, silicon is formed. Then, in the fourth photolithography process, the third conductive thin film is patterned to form the source electrode 50 and the drain electrode 51. Then, though it is not clear from the drawings attached to Japanese Unexamined Patent Publication No. 97386/1985, in the fifth photolithography process, the gate insulating film is patterned and the contact hole for connecting the gate line to gate-side driving IC is formed.
In this conventional example, a method for manufacturing the TFT array comprising five processes containing the photolithography process, respectively, in this way is disclosed. For the effects, it is described that by making a semiconductor layer be a semiconductor layer 48 formed in a continuous profile from the portion where the source electrode 50 is formed to the portion where the TFT channel is formed, generation of disconnection of source line can be reduced, short-circuiting between the gate line and the source line can be reduced, and the contact resistance between the source electrode and the semiconductor layer in TFT can be reduced.
FIGS. 18(a), 18(b) and 18(c) show cross-sectional illustrations of the main portion of the TFT array substrate manufactured in the fifth photolithography process disclosed in the seventh embodiment of Japanese Unexamined Patent Publication No. 50308/1996. FIG. 18(a) shows a main portion of the source TCP connecting electrode, FIG. 18(b) a main portion of the display pixel, and FIG. 18(c) part of gate line. In FIGS. 18(a), 18(b) and 18(c), numeral 57 designates a channel portion, 58 a gate electrode, 59 gate line, 60 a gate insulating film, 61 a semiconductor active film, an ohmic contact film, 63 a source electrode, 64 a source line, 65 a drain electrode, 66 a passivation film, 67, 68, and 69 contact holes, 70 a transparent pixel electrode, and 71 a source TCP connecting electrode.
In this conventional example, first, on a transparent substrate, the first conductive metal thin film of chromium, molybdenum, aluminum is formed about 100 nm thick. Then, in the first photolithography process, the first conductive metal thin film is patterned and the gate electrode 58 and the gate line 59 are formed In this event, in the case the first conductive metal thin film is chromium, wet etching treatment is carried out using an etchant comprising, for example, (NH.sub.4).sub.2 [Ce(NH.sub.3).sub.6 ] and HNO.sub.3 and H.sub.2 O. Then, for the first insulating film, the SiNx film, for the semiconductor active film 61, the a-Si film, for the ohmic contact film 62, the n.sup.+ a-Si film are laminated to film thickness of about 300 nm, 100 nm, and 20 nm, respectively.
Next, in the second photolithography process, the semiconductor active film 61 and ohmic contact film 62 are patterned in the form of island with the semiconductor portion separated from other portion above the gate electrode. In this event, for example, the semiconductor active film and ohmic contact film are wet-etching treated with the etchant comprising, for example, HF and HNO.sub.3. Then, the second metal thin film comprising titanium is formed about 300 nm in thickness.
Next, in the third photolithography process, the second metal thin film and ohmic contact film are patterned to form the source electrode 63, source line 64, drain electrode 65, and channel portion 57. In this event, for example, the second metal thin film and ohmic contact film are wet-etching treated with the etchant comprising, for example, HF and H.sub.2 O. Then, the passivation film 66 is formed about 400 nm in thickness by the methods such as the plasma CVD method.
Then, in the fourth photolithography process, the passivation film is patterned to form a contact hole 67 connecting to the drain electrode 65, a contact hole 67 connecting to the gate line 59, and a contact hole 69 connecting to the source line 64. In this event, the passivation film is etching-treated by dry etching using etching gas comprising, for example, SF.sub.6 and O.sub.2. Then, a transparent conductive film comprising ITO (indium tin oxide) is formed about 150 nm in thickness.
Then, in the fifth photolithography process, a transparent conductive film is patterned and a terminal for connecting the transparent pixel electrode 70 and the source line is formed. In this event, for example, using the etchant comprising, for example, HCl and HNO.sub.3 and H.sub.2 O, the ITO film is wet-etching treated.
In this conventional example, a method for manufacturing the TFT array in five processes, each containing the photolithography process, is disclosed, and as the effect, it is stated that because the number of processes can be shortened to five processes, each containing the photolithography process, the yield is improved and manufacturing cost is reduced, and because there is no passivation film on the transparent pixel electrode, voltage can be efficiently applied to the liquid crystal layer, and because the transparent pixel electrode and source line and gate line are formed separated by the insulating film, respectively, there is no fear of generating short-circuiting among source lines or gate lines due to defective formation of the transparent pixel electrode.
For the effects of this conventional example, there described are (1) when the first conductive metal thin film is formed using the laminated film with metal thin film and the barrier film comprising the material difficult to be oxidized or the material which is to be solid-solution as conductive oxide for the transparent conductive film, the barrier film further takes oxidation prevention effect and the contact capability of these films with other conductive films can be secured, and the problem of delayed signal is difficult to occur, and (2) the use of aluminum or tantalum with good conductivity as metal thin film can decrease the film thickness of the metal thin film, improve the step coverage of the whole TFT element, and the yield can be improved.
FIG. 19 shows the cross-sectional illustration of the main portion of the contact terminal portion with TCP of the conventional TFT array substrate disclosed in Japanese Unexamined Patent Publication No. 92496/1995. In FIG. 19, numeral 72 designates the undercoat film, 73 a lead-out electrode, 74 a gate insulating film, 75 a transparent conductive film, 76 an insulating protection film, and 77 a TCP connection range.
In this conventional example, first of all, on the overall insulating substrate, the undercoat film 72 comprising silicon dioxide (SiO.sub.2) or tantalum oxide (TaOx) is formed. Then, the first metal thin film comprising aluminum or aluminum alloy is formed, and patterned in the first photolithography process to form the lead-out electrode 73. Then, the gate insulating film 74 is formed on the whole surface. Next, above the gate electrode comprising the first metal thin film of TFT portion provided to the display pixel, the silicon semiconductor layer and interlayer insulating film for channel protection film are formed.
Then, in the second photolithography process, above the gate electrode, the channel protection film is patterned. Then, n.sup.+ silicon film is formed.
In addition, in the third photolithography process, the n.sup.+ silicon film of the TFT portion and silicon semiconductor layer are patterned. Then the transparent conductive film is formed.
Then, in the fourth photolithography process, the transparent conductive film 75 is patterned so as to remain on the peripheral portion of the display electrode of the pixel portion and lead-out electrode 73. Then, the second metal thin film comprising titanium or aluminum is formed for the source electrode and drain electrode of the TFT portion provided to the display pixel, and in the fifth photolithography process, the film is patterned. Then, the insulating protection film 76 is formed, and in the 6th photolithography process, an opening portion is formed at the lead-out electrode portion by dry etching. TCP is connected to the position slightly deviated from the opening portion of the lead-out electrode portion to the side opposite to the display portion according to the disclosed drawings.
In this conventional example, a method for manufacturing TFT array substrates forming the TCP connecting terminal portion in the manufacturing process including six photolithography processes in this way, and as the effects, it is stated that disconnection of the lead-out electrode can be eliminated by stopping the propagation of corrosion of the first metal thin film generated from the opening portion of the lead-out electrode by the gate insulating film and the transparent conductive film installed to the peripheral portion of the lead-out electrode.
When the TFT array is manufactured using the conventional technique disclosed in Japanese Unexamined Patent Publication No. 97386/1985, it is necessary to form the semiconductor film 48, pixel electrode 49, are source electrode 50 in the same layer on the gate insulating film. Due to defective patterns generated in actual manufacturing process, there generated are troubles in that defects are apt to occur because short-circuiting occurs between pixel electrode and source line or short-circuiting occurs between the semiconductor layer and the pixel electrode. Short-circuiting between the pixel electrode and the source line appears as point defect at the time of display, while short-circuiting between the semiconductor layer and the pixel electrode appears as point defect when light is irradiated.
In this conventional technique, because the TFT channel portion is exposed, the TFT OFF current increases, giving rise to nonconformity in that the display quality is degraded. In addition, line of the auxiliary capacity electrode is unknown in the range of the detailed explanation disclosed in this conventional technique, and in the case the electrode is formed with known technique as common electrode, a contact hole for connection with the third conductive thin film must be formed in the periphery of the display portion. In this event, one photolithography process is added and a total of six photolithography processes were required.
In the conventional technique disclosed in Japanese Unexamined Patent Publication No. 50308/1996, when the TFT array is manufactured by the illustrated process, there occurred is nonconformity in that pin hole is generated because the silicon nitride (SiNx) film which is the first insulating film of the bottom layer portion of the area free of the semiconductor active film and ohmic contact film is also subject to the etchant when wet-etching treatment is carried out with the etchant comprising HF and HNO.sub.3 when the semiconductor active film 61 and ohmic contact film 62 are patterned above the gate electrode in the form of island with the semiconductor portion separated from other portions. And nonconformity was generated in that the first insulating SiNx film of the bottom layer portion around the pattern of the left semiconductor active film and ohmic contact film are etched, the profile of the semiconductor active film and ohmic contact film becomes the flaw and causes stepping (the second metal thin film causes tearing of pattern with the step difference as a boundary where there is a step difference).
There is nonconformity in that the etchant is likely to penetrate in the step difference portion around the patterns of semiconductor active film and ohmic contact film when the second metal thin film is patterned by the wet etching treatment even when the semiconductor active film 61 and the ohmic contact 62 are dry-etching treated when the semiconductor active film 61 and the ohmic contact 62 are patterned above the gate electrode and in the form of island with the semiconductor portion separated from other portions in the second photolithography process. In particular, there is nonconformity in that the so-called stepping markedly occurs when the standing time from film-forming of the second metal thin film to the photolithography process is not shortened.
In the third photolithography process, in the case the second metal thin film and ohmic contact film are subjected to wet-etching with the etchant comprising HF and H.sub.2 O when the second metal thin film and ohmic contact film are patterned to form the source electrode 63, source line 64, drain electrode 65, and channel portion 57, a process for wet-etching treating the semiconductor active film and ohmic contact film is required. In this process, pinholes are generated because the first insulating SiNx film of the bottom layer portion in the region where no semiconductor active film and ohmic contact film remain are also exposed to the etchant. In addition, of the circumference of patterns of the left semiconductor active film and ohmic contact film, the first insulating SiNx film of the bottom layer portion where no source electrode 63 and drain electrode 65 are left is etched and the profile of the semiconductor active film and the ohmic contact film becomes a flaw, and because this flaw portion is unable to sufficiently cover with the passivation film, the OFF current of TFT increases, and the display quality may be degraded. There occurs nonconformity in that the pixel transparent electrode generates stepping around the pattern of the semiconductor active film and ohmic contact film to generate a defect, or the electrochemical reactions rapidly take place, the second metal thin film dissolves, and disconnection of source line and source electrode is generated, the transparent electrode dissolves to generate defects when a specified signal voltage is applied to TFT array to drive due to the remaining etchant at the flaw portion around patterns of the semiconductor active film and ohmic contact film.
Because to the TFT array substrate manufactured by using the process for manufacturing disclosed in the 7th embodiment of Japanese Unexamined Patent Publication No. 50308/1996, no auxiliary capacity is provided in parallel to the liquid crystal capacity (capacity formed with the liquid crystal material put in-between the display pixel electrode and the opposite substrate), there generated is nonconformity with respect to display quality in which the display causes image tricking or the display causes luminance distribution.
When the TFT array substrate is manufactured using the conventional technique disclosed in Japanese Unexamined Patent Publication No. 92496/1995, according to the disclosed drawings, because TCP is connected to the position slightly deviated to the side opposite to the display portion from the opening portion of the lead-out electrode portion, corrosion of the first metal thin film tends to develop from the portion not covered with TCP of the opening portion of the lead-out electrode due to the influence of humidity. There generated is nonconformity in that though this corrosion may be stopped by the gate insulating film and transparent conductive film provided on the periphery of the lead-out electrode in a short term, but in the long term, it results in disconnection, or connection resistance increases between TCP and the display portion line, if not disconnection, and changes in display characteristics is brought about due to signal distortion.
In the conventional technique, in order to form the transparent conductive film with high reliability to the electrical probing at the TCP connecting terminal portion, it is necessary to add photolithography processes for forming the transparent conductive film after fabricating the construction disclosed in FIG. 19, and patterning this film. Consequently, in the range of the disclosed technique, there generated is nonconformity in which erroneous judgment is likely to result in because the first metal thin film must be directly probed when a process is applied for providing electric probing at the TCP connecting terminal portion with the inspection apparatus after fabricating the TFT array substrate, inspecting the TFT characteristics of the display portion, and screen-eliminating defective substrates to reduce the quantity of opposite substrates. And even in this conventional example, six photolithography processes are required.